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Digital IC Backend Physical Design Engineer (All Levels)

Digital IC Backend Physical Design Engineer (All Levels)

On site

Cambridge, United kingdom

Senior

Full Time

06-10-2025

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Skills

Python Perl Problem-solving Attention to detail

Job Specifications

Company Description

Rigpa is an exciting fabless chip design start-up focusing on the next-generation AI ASIC chips. These chips are designed to accelerate future AI applications at 10x faster speed with a fraction of the power.

As we hit the limits of speed, cost, and scale on today's chips, specialized chips are inevitable. Join us in solving the most important problem in AI.

Role Description

This is a full-time on-site role for a Digital IC Physical Backend Design Engineer at all levels. The role is located in Cambridge or Edinburgh.

Our AI chips target advanced FinFET and beyond nodes. We need physical design engineers who can take complex AI SoCs from netlist to GDSII while meeting power, performance and area targets.

Qualifications

Experience in Digital Designs, Digital Circuit Design, and Circuit Design
Skills in Digital IC Design and RTL Coding
Ability to collaborate effectively within a team and work on-site
Strong problem-solving skills and attention to detail
Bachelor's or Master's degree in Electrical Engineering or related field
Experience in AI chip design is a plus

Join our silicon design team working on cutting-edge AI ASIC. You will help define and implement the digital microarchitecture of the next-gen AI chip.

Key responsibilities

Perform synthesis, floor planning, placement, clock-tree synthesis, routing and optimisation for high-speed AI ASICs on sub-7-nm technologies.
Define and drive physical design strategies, including partitioning, hierarchical floorplans, pin placement and power grid design, to meet timing and layout constraints.
Generate and refine timing constraints (SDC), run static timing analysis (STA) and close timing across process corners and voltage variations.
Work closely with RTL design, synthesis, verification and DFT teams to implement ECOs and resolve functional and timing issues during integration.
Perform physical verification (DRC, LVS, IR-drop, electromigration) and sign-off; develop and automate P&R flows using Cadence/Synopsys/Mentor tools and scripting languages

Ideal qualifications

7+ years of experience in backend physical design and tape-out for advanced nodes (7 nm or below).
Deep understanding of place-and-route flows, timing closure, power optimisation and clock-tree synthesis.
Proficiency with EDA tools (Cadence Innovus, Synopsys ICC2, Mentor Calibre) and scripting languages such as TCL, Perl or Python for automation.
Knowledge of low-power design techniques (UPF/CPF) and challenges associated with FinFET process technology.
Excellent problem-solving skills and ability to work in a collaborative, cross-disciplinary team.

Join us in building the most advanced hardware for superintelligence.

Looking for an opportunity but don't see a role? Reach out to hr@rigpa.ai

About the Company

Rigpa is an exciting fabless chip design start-up focusing on the next-generation AI chips to accelerate future AI applications at 10x faster speed with a fraction of the power. Know more